Meng-Fan Chang

According to our database1, Meng-Fan Chang authored at least 106 papers between 1997 and 2019.

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Bibliography

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications.
IEEE Trans. on Circuits and Systems, 2019

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.
IEEE Trans. on Circuits and Systems, 2019

A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation.
J. Solid-State Circuits, 2019

Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration.
IEEE Trans. VLSI Syst., 2018

A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories.
IEEE Trans. VLSI Syst., 2018

A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip.
IEEE Trans. on Circuits and Systems, 2018

Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM.
IEEE Access, 2018

Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 28nm 32Kb embedded 2T2MTJ STT-MRAM macro with 1.3ns read-access time for fast and reliable read applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning.
Proceedings of the International Conference on Computer-Aided Design, 2018

Parallelizing SRAM arrays with customized bit-cell for binary neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

A 28mn 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology.
IEEE Trans. VLSI Syst., 2017

A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata.
IEEE Trans. VLSI Syst., 2017

Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache.
IEEE Trans. on Circuits and Systems, 2017

Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops.
IEEE Trans. on Circuits and Systems, 2017

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.
J. Solid-State Circuits, 2017

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.
J. Solid-State Circuits, 2017

A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications.
J. Solid-State Circuits, 2017

A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing.
J. Solid-State Circuits, 2017

A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme.
J. Solid-State Circuits, 2017

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing.
J. Solid-State Circuits, 2016

Design of nonvolatile processors and applications.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Nonvolatile memory design based on ferroelectric FETs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
Set-Triggered-Parallel-Reset Memristor Logic for High-Density Heterogeneous-Integration Friendly Normally Off Applications.
IEEE Trans. on Circuits and Systems, 2015

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations.
J. Solid-State Circuits, 2015

Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations.
J. Solid-State Circuits, 2015

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros.
J. Solid-State Circuits, 2015

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications.
Proceedings of the Symposium on VLSI Circuits, 2015

An embedded ReRAM using a small-offset sense amplifier for low-voltage operations.
Proceedings of the VLSI Design, Automation and Test, 2015

17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Energy-efficient non-volatile TCAM search engine design using priority-decision in memory technology for DPI.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Ambient energy harvesting nonvolatile processors: from circuit to system.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia.
IEEE Trans. Biomed. Circuits and Systems, 2014

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme.
J. Solid-State Circuits, 2014

ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing.
Proceedings of the Symposium on VLSI Circuits, 2014

A signal acquisition and processing chip with built-in cluster for chemiresistive gas sensor array.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A nonvolatile look-up table using ReRAM for reconfigurable logic.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement.
J. Solid-State Circuits, 2013

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro.
J. Solid-State Circuits, 2013

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory.
J. Solid-State Circuits, 2013

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.
J. Solid-State Circuits, 2013

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques.
J. Solid-State Circuits, 2013

Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan.
IEEE Access, 2013

Special session 4C: Hot topic 3D-IC design and test.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012
A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances.
IEEE Trans. on Circuits and Systems, 2012

Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications.
J. Solid-State Circuits, 2012

Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM.
J. Solid-State Circuits, 2012

A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.
Proceedings of the Symposium on VLSI Circuits, 2012

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System.
IEEE Trans. Biomed. Circuits and Systems, 2011

A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.
J. Solid-State Circuits, 2011

A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications.
J. Solid-State Circuits, 2011

Fast-Write Resistive RAM (RRAM) for Embedded Applications.
IEEE Design & Test of Computers, 2011

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM).
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded write/ read Stability and Speed-Area-Wise Array for Sub-0.5-V Chips.
IEEE Trans. on Circuits and Systems, 2010

Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements.
J. Solid-State Circuits, 2010

A Differential Data-Aware Power-Supplied (D 2 AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications.
J. Solid-State Circuits, 2010

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM.
IEEE Trans. VLSI Syst., 2009

Wide VDD Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems.
IEEE Trans. on Circuits and Systems, 2009

A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme.
J. Solid-State Circuits, 2009

2006
Crosstalk-insensitive via-programming ROMs using content-aware design framework.
IEEE Trans. on Circuits and Systems, 2006

SRAM Cell Current in Low Leakage Design.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

2005
Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC.
VLSI Signal Processing, 2005

Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

2004
Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

1997
Power-Area Trade-Offs in Divided Word Line Memory Arrays.
Journal of Circuits, Systems, and Computers, 1997


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