Ren-Shuo Liu

According to our database1, Ren-Shuo Liu authored at least 27 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020

15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

OPTR: Order-Preserving Translation and Recovery Design for SSDs with a Standard Block Device Interface.
Proceedings of the 2019 USENIX Annual Technical Conference, 2019

Long-Term JPEG Data Protection and Recovery for NAND Flash-Based Solid-State Storage.
Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN).
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

AIP: Saving the DRAM Access Energy of CNNs Using Approximate Inner Products.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

DI-SSD: Desymmetrized interconnection architecture and dynamic timing calibration for solid-state drives.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality.
IEEE Trans. Computers, 2016

2014
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

NVM duet: unified working memory and persistent store architecture.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
DuraCache: a durable SSD cache using MLC NAND flash.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Optimizing NAND flash-based SSDs via retention relaxation.
Proceedings of the 10th USENIX conference on File and Storage Technologies, 2012

2010
Parallelization and characterization of GARCH option pricing on GPUs.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010


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