Ka-Fai Un
Orcid: 0000-0002-7574-4755
According to our database1,
Ka-Fai Un
authored at least 24 papers
between 2008 and 2024.
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Bibliography
2024
A 0.05-mm<sup>2</sup> 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS.
IEEE J. Solid State Circuits, February, 2024
17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM.
IEEE J. Solid State Circuits, November, 2023
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 108-nW 0.8-mm<sup>2</sup> Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 108nW 0.8mm<sup>2</sup> Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
2019
A 0.12-mm<sup>2</sup> 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Overview of Recent Development on Wireless Sensing Circuits and Systems for Healthcare and Biomedical Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
2016
Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitter.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2013
A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A 53-to-75-mW, 59.3-dB HRR, TV-Band White-Space Transmitter Using a Low-Frequency Reference LO in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013
2011
Proceedings of EUROCON 2011, 2011
2010
Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
An Open-loop Octave-phase Local-oscillator Generator with High-precision Correlated Phases for VHF/UHF Mobile-TV Tuners.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
A DC-offset-compensated, CT/DT hybrid filter with process-insensitive cutoff and low in-band group-delay variation for WLAN receivers.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008