Kang-Yu Chang

According to our database1, Kang-Yu Chang authored at least 7 papers between 2006 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2022
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

2021
A Reconfigurable In-SRAM Computing Architecture for DCNN Applications.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

On Reconfiguring Memory-Centric AI Edge Devices for CIM.
Proceedings of the 18th International SoC Design Conference, 2021

A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2006
Level Selection Based 4-PAM Transmitter for Chip to Chip Communication.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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