Kang-Yu Chang

According to our database¹, Kang-Yu Chang authored at least 8 papers between 2006 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2022

An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications.

[BibT_eX]

[DOI]

Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

On Optimizing Capacitor Array Design for Advanced Node SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Synthesis, 2022

2021

A Reconfigurable In-SRAM Computing Architecture for DCNN Applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

On Reconfiguring Memory-Centric AI Edge Devices for CIM.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO.

[BibT_eX]

[DOI]

Chia-Chen Chang

Yu-Tung Chin

Hossameldin A. Ibrahim

Kang-Yu Chang

Shyh-Jye Jou

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2006

Level Selection Based 4-PAM Transmitter for Chip to Chip Communication.

[BibT_eX]

[DOI]

Kang-Yu Chang

Zhi-Ming Lin

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Kang-Yu Chang

Timeline

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Bibliography

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