According to our database1, Kang-Yu Chang authored at least 7 papers between 2006 and 2022.
Legend:Book In proceedings Article PhD thesis Other
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021
Proceedings of the 18th International SoC Design Conference, 2021
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006