Kazuyuki Tanimura

According to our database, Kazuyuki Tanimura authored at least 7 papers between 2008 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays.

Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil D. Dutt

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design.

Kazuyuki Tanimura, Nikil D. Dutt

IEEE Embed. Syst. Lett., 2012

LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks.

Kazuyuki Tanimura, Nikil D. Dutt

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Slack-aware scheduling on Coarse Grained Reconfigurable Arrays.

Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil D. Dutt

Proceedings of the Design, Automation and Test in Europe, 2011

2010

ExCCel: Exploration of Complementary Cells for Efficient DPA Attack Resistivity.

Kazuyuki Tanimura, Nikil D. Dutt

Proceedings of the HOST 2010, 2010

2009

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in <i>GF</i>(<i>P</i>) and <i>GF</i>(2^<i>n</i>).

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2ⁿ).

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008