Shunitsu Kohara

According to our database, Shunitsu Kohara authored at least 6 papers between 2005 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

An integrated optimization framework for reducing the energy consumption of embedded real-time applications.

Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2009

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in <i>GF</i>(<i>P</i>) and <i>GF</i>(2^<i>n</i>).

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures.

Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IPSJ Trans. Syst. LSI Des. Methodol., 2008

Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2ⁿ).

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2006

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs.

Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A processor core synthesis system in IP-based SoC design.

Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005