Ryuji Yamashita
According to our database1,
Ryuji Yamashita authored at least 9 papers
between 2012 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2026
A 29-Gb/mm<sup>2</sup> 1-Tb 3-b/Cell 3-D Flash Memory With CMOS Direct Bonded Array (CBA) Technology.
IEEE J. Solid State Circuits, January, 2026
A 2Tb 4b/Cell 6-Plane 3D-Flash Memory with 37.6Gb/mm<sup>2</sup> Bit Density and >85MB/s Write Throughput.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
IEEE J. Solid State Circuits, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2013
A 19 nm 112.8 mm<sup>2</sup> 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface.
IEEE J. Solid State Circuits, 2013
2012
A 19nm 112.8mm<sup>2</sup> 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012