Keiichi Tokutome

According to our database, Keiichi Tokutome authored at least 3 papers between 2009 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.

Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Proceedings of the Symposium on VLSI Circuits, 2012

2009

High Speed 1.1-µm-Range InGaAs-Based VCSELs.

Naofumi Suzuki, Takayoshi Anan, Hiroshi Hatakeyama, Kimiyoshi Fukatsu, Kenichiro Yashiki, Keiichi Tokutome, Takeshi Akagawa, Masayoshi Tsuji

IEICE Trans. Electron., 2009