Shoji Ikeda
Orcid: 0000-0002-3925-4089
According to our database1,
Shoji Ikeda
authored at least 22 papers
between 2007 and 2022.
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Bibliography
2022
Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2021
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.
IEEE J. Solid State Circuits, 2021
2020
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits, 2019
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2016
Proc. IEEE, 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
2015
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.
IEEE J. Solid State Circuits, 2015
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torque.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.
IEICE Electron. Express, 2013
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.
Proceedings of the Symposium on VLSI Circuits, 2012
A 3.14 um<sup>2</sup> 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture.
Proceedings of the Symposium on VLSI Circuits, 2012
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2010
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme.
IEEE J. Solid State Circuits, 2010
Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit.
IEICE Trans. Electron., 2010
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits.
IEICE Trans. Electron., 2010
2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read.
IEEE J. Solid State Circuits, 2008
2007
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007