Toru Kisuki

According to our database1, Toru Kisuki authored at least 8 papers between 1996 and 2004.

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Bibliography

2004
The effect of cache models on iterative compilation for combined tiling and unrolling.
Concurr. Comput. Pract. Exp., 2004

2003
Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation.
J. Supercomput., 2003

2002
Iterative Compilation.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

2001
Cache Models for Iterative Compilation.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

1999
A Feasibility Study in Iterative Compilation.
Proceedings of the High Performance Computing, Second International Symposium, 1999

OCEANS - Optimising Compilers for Embedded Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1997
Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors.
Proceedings of the Euro-Par '97 Parallel Processing, 1997

1996
ATTEMPT-1: A Reconfigurable Multiprocessor Testbed.
Proceedings of the Field-Programmable Logic, 1996


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