Ken'ichi Shimomura

According to our database, Ken'ichi Shimomura authored at least 4 papers between 1993 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique.

Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma

IEEE J. Solid State Circuits, 1997

1996

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.

Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe

IEEE J. Solid State Circuits, 1996

A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.

Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1993

Fuzzy inference and fuzzy inference processor.

Kazuo Nakamura, Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Takeshi Tokuda

IEEE Micro, 1993