Hiroki Shimano

According to our database1, Hiroki Shimano authored at least 7 papers between 1996 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform.
IEICE Trans. Electron., 2009

2007
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory.
IEEE J. Solid State Circuits, 2007

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs.
IEEE J. Solid State Circuits, 2007

A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform.
IEICE Trans. Electron., 2007

1997
A 1-V 46-ns 16-Mb SOI-DRAM with body control technique.
IEEE J. Solid State Circuits, 1997

1996
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.
IEEE J. Solid State Circuits, 1996

A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996


  Loading...