Satoshi Yamakawa
According to our database1,
Satoshi Yamakawa
authored at least 7 papers
between 1996 and 2020.
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Bibliography
2020
IEEE Access, 2020
2018
Effect of lanthanum silicate interface layer on the electrical characteristics of 4H-SiC metal-oxide-semiconductor capacitors.
Microelectron. Reliab., 2018
Improvement of SiO<sub>2</sub>/4H-SiC Interface properties by post-metallization annealing.
Microelectron. Reliab., 2018
2008
Low-current consumption CMOS comparator using charge-storage amplifier for A/D converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2004
21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs).
IEEE J. Solid State Circuits, 2004
2003
Proceedings of the 20th IEEE/11th NASA Goddard Conference on Mass Storage Systems and Technologies, 2003
1996
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.
IEEE J. Solid State Circuits, 1996