Khushboo Qayyum
Orcid: 0009-0004-7408-8399
According to our database1,
Khushboo Qayyum
authored at least 13 papers
between 2014 and 2025.
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Bibliography
2025
Correct and Verify - CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders With Correct Carry Bits.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2025
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025
Proceedings of the IEEE European Test Symposium, 2025
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2025
2024
veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024
EnR: extend and reduce methodology to enable formal verification of truncated adders.
it Inf. Technol., 2024
Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 33rd IEEE Asian Test Symposium, 2024
2015
Proceedings of the 2015 IEEE International Conference on Smart Grid Communications, 2015
Proceedings of the 2015 ACM Sixth International Conference on Future Energy Systems, 2015
2014
Proceedings of the Fifth International Conference on Future Energy Systems, 2014