Grace Li Zhang

CoRR, 2023

Logic Design of Neural Networks for High-Throughput and Low-Power Applications.

[BibT_eX]

[DOI]

CoRR, 2023

Expressivity Enhancement with Efficient Quadratic Neurons for Convolutional Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2023

NearUni: Near-Unitary Training for Efficient Optical Neural Networks.

[BibT_eX]

[DOI]

Amro Eldebiky

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Class-based Quantization for Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Countering Uncertainties in In-Memory-Computing Platforms with Statistical Training, Accuracy Compensation and Recursive Test.

[BibT_eX]

[DOI]

Amro Eldebiky

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

VirtualSync+: Timing Optimization With Virtual Synchronization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Aging Aware Retraining for Memristor-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming.

[BibT_eX]

[DOI]

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

An Efficient Programming Framework for Memristor-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Energy-Aware Designs of Ferroelectric Ternary Content Addressable Memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Bayesian Inference Based Robust Computing on Memristor Crossbar.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).

[BibT_eX]

[DOI]

CoRR, 2020

Countering Variations and Thermal Effects for Accurate Optical Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Reliable and Robust RRAM-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Timing Resilience for Efficient and Secure Circuits.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019

EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Application of machine learning methods in post-silicon yield improvement.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2016

PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Sampling-based buffer insertion for post-silicon yield improvement under process variability.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers.

[BibT_eX]

[DOI]