Kinshuk Khare

According to our database, Kinshuk Khare authored at least 2 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme.

Hidehiro Fujiwara, Wei-Chang Zhao, Kinshuk Khare, Yi-Hsin Nien, Chih-Yu Lin, Cheng-Han Lin, Shan-Ru Liao, Kenta Torigoe, Shirleen Xia, Yuichiro Ishii, Yao-Yi Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm² and 3.78Mb/mm² Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.

Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024