Tan-Li Chou

According to our database, Tan-Li Chou authored at least 18 papers between 1994 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm² and 3.78Mb/mm² Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.

Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.

Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.

Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, Cheng-Han Lu, Yu-Lin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng-Hsiung Kuo, Tan-Li Chou, Chia-Yu Wang, J. J. Wu, Roger Wang, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications.

Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.

Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.

Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Cheng Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2001

Integrated power supply planning and floorplanning.

I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong

Proceedings of ASP-DAC 2001, 2001

2000

Estimating Circuit Activity in Combinational CMOS Digital Circuits.

Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou

IEEE Des. Test Comput., 2000

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion.

I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong

Proceedings of the 2000 International Symposium on Physical Design, 2000

1998

Efficient statistical approach to estimate power considering uncertain properties of primary inputs.

Zhanping Chen, Kaushik Roy, Tan-Li Chou

IEEE Trans. Very Large Scale Integr. Syst., 1998

Power Estimation Under Uncertain Delays.

Tan-Li Chou, Kaushik Roy

Integr. Comput. Aided Eng., 1998

1997

Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique.

Priya Patil, Tan-Li Chou, Kaushik Roy, Rabindra Roy

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.

Zhanping Chen, Kaushik Roy, Tan-Li Chou

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Accurate power estimation of CMOS sequential circuits.

Tan-Li Chou, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 1996

Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching.

Tan-Li Chou, Kaushik Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Estimation of sequential circuit activity considering spatial and temporal correlations.

Tan-Li Chou, Kaushik Roy

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Statistical estimation of sequential circuit activity.

Tan-Li Chou, Kaushik Roy

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Estimation of circuit activity considering signal correlations and simultaneous switching.

Tan-Li Chou, Kaushik Roy, Sharat Prasad

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994