Haruki Mori
Orcid: 0000-0002-8149-393X
According to our database1,
Haruki Mori
authored at least 17 papers
between 2015 and 2024.
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Bibliography
2024
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm<sup>2</sup> and 3.78Mb/mm<sup>2</sup> Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 5-nm 254-TOPS/W 221-TOPS/mm<sup>2</sup> Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
An 89TOPS/W and 16.3TOPS/mm<sup>2</sup> All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 2018 IEEE Global Conference on Signal and Information Processing, 2018
2017
A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning.
Proceedings of the 27th IEEE International Workshop on Machine Learning for Signal Processing, 2017
2016
A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor.
IEICE Trans. Electron., 2016
An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015