Konstantinos Tovletoglou

Orcid: 0000-0002-1513-3143

According to our database1, Konstantinos Tovletoglou authored at least 14 papers between 2017 and 2023.

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Bibliography

2023
Concurrent GCs and Modern Java Workloads: A Cache Perspective.
Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management, 2023

2022
On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study.
IEEE Trans. Sustain. Comput., 2022

2021
Revealing DRAM Operating GuardBands Through Workload-Aware Error Predictive Modeling.
IEEE Trans. Computers, 2021

2020
HaRMony: Heterogeneous-Reliability Memory and QoS-Aware Energy Management on Virtualized Servers.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Shimmer: Implementing a Heterogeneous-Reliability DRAM Framework on a Commodity Server.
IEEE Comput. Archit. Lett., 2019

Workload-Aware DRAM Error Prediction using Machine Learning.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

2018
Int. J. High Perform. Comput. Appl., 2018

Characterization of HPC workloads on an ARMv8 based server under relaxed DRAM refresh and thermal stress.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018


2017
Dependency-Aware Rollback and Checkpoint-Restart for Distributed Task-Based Runtimes.
CoRR, 2017

Access-aware DRAM failure-rate estimation under relaxed refresh operations.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017


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