Manolis Kaliorakis

According to our database1, Manolis Kaliorakis authored at least 20 papers between 2013 and 2019.

Collaborative distances:



In proceedings 
PhD thesis 




SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
IEEE Trans. Computers, 2019

Statistical Analysis of Multicore CPUs Operation in Scaled Voltage Conditions.
Computer Architecture Letters, 2018

Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018

Performance-aware reliability assessment of heterogeneous chips.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Harnessing voltage margins for energy efficiency in multicore CPUs.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Voltage margins identification on commercial x86-64 multicore microprocessors.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2017

Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Cross-layer system reliability assessment framework for hardware faults.
Proceedings of the 2016 IEEE International Test Conference, 2016

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Bayesian network early reliability evaluation analysis for both permanent and transient faults.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Differential Fault Injection on Microarchitectural Simulators.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

A Bayesian model for system level reliability estimation.
Proceedings of the 20th IEEE European Test Symposium, 2015

Accelerated microarchitectural Fault Injection-based reliability assessment.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Accelerated online error detection in many-core microprocessor architectures.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Versatile architecture-level fault injection framework for reliability evaluation: A first report.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Online error detection in multiprocessor chips: A test scheduling study.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013