Hyung Gyu Lee
According to our database1,
Hyung Gyu Lee
authored at least 49 papers
between 2000 and 2022.
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Bibliography
2022
Sensors, 2022
2020
Sensors, 2020
Sensors, 2020
2019
A Task Failure Rate Aware Dual-Channel Solar Power System for Nonvolatile Sensor Nodes.
ACM Trans. Embed. Comput. Syst., 2019
An Ultra-Low Energy Human Activity Recognition Accelerator for Wearable Health Applications.
ACM Trans. Embed. Comput. Syst., 2019
IEEE Des. Test, 2019
Sensor-Classifier Co-Optimization for Wearable Human Activity Recognition Applications.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019
Tumbler: Energy Efficient Task Scheduling for Dual-Channel Solar-Powered Sensor Nodes.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Puppet: Energy Efficient Task Mapping For Storage-Less and Converter-Less Solar-Powered Non-Volatile Sensor Nodes.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
ACM Trans. Design Autom. Electr. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
2016
Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 13th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2016
2015
IEEE Trans. Computers, 2015
Design space exploration of row buffer architecture for phase change memory with LPDDR2-NVM interface.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
Des. Autom. Embed. Syst., 2014
A high-efficiency dual-channel photovoltaic power system for nonvolatile sensor nodes.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014
Storage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessor.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era.
ACM Trans. Archit. Code Optim., 2013
Sharded Router: A novel on-chip router architecture employing bandwidth sharding and stealing.
Parallel Comput., 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
A Compression-Based Hybrid MLC/SLC Management Technique for Phase-Change Memory Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching.
Proceedings of the Computing Frontiers Conference, CF'12, 2012
2011
Hardware-Based Job Queue Management for Manycore Architectures and OpenMP Environments.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
A High-Performance and Energy-Efficient Virtually Tagged Stack Cache Architecture for Multi-core Environments.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011
2010
IEEE Trans. Consumer Electron., 2010
2008
A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems.
Proceedings of the 8th ACM & IEEE International conference on Embedded software, 2008
2007
On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches.
ACM Trans. Design Autom. Electr. Syst., 2007
2006
Communication architecture optimization: making the shortest path shorter in regular networks-on-chip.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
J. Low Power Electron., 2005
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005
2004
2003
ACM Trans. Embed. Comput. Syst., 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
2002
Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors].
IEEE Trans. Very Large Scale Integr. Syst., 2002
Proceedings of the 39th Design Automation Conference, 2002
2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000