Jae-Woo Im

According to our database1, Jae-Woo Im authored at least 7 papers between 2006 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A 28-Gb/mm<sup>2</sup> 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs.
IEEE J. Solid State Circuits, January, 2026

2025

2022
Toward Heterogeneous Virtual Platforms For Early SW Development.
Proceedings of the 19th International SoC Design Conference, 2022

2021
Early HW/SW Co-Verification Using Virtual Platforms.
Proceedings of the 18th International SoC Design Conference, 2021

2016
A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate.
IEEE J. Solid State Circuits, 2016

2015

2006
Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006


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