Chris Winstead

According to our database1, Chris Winstead authored at least 48 papers between 2001 and 2020.

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Bibliography

2020
Decoding LDPC Codes with Probabilistic Local Maximum Likelihood Bit Flipping.
Proceedings of the International Symposium on Information Theory and Its Applications, 2020

2019
A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Resilient Control Design for Vehicular Platooning in an Adversarial Environment.
Proceedings of the 2019 American Control Conference, 2019

2018
Analysis of Friendly Jamming for Secure Location Verification of Vehicles for Intelligent Highways.
IEEE Trans. Veh. Technol., 2018

Collaborative Attacks on Autonomous Vehicle Platooning.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Reachable Set Analysis of Vehicular Platooning in Adversarial Environment.
Proceedings of the 2018 Annual American Control Conference, 2018

Identification of the Attacker in Cyber-Physical Systems with an Application to Vehicular Platooning in Adversarial Environment.
Proceedings of the 2018 Annual American Control Conference, 2018

2017
Viability of Using Shadows Cast by Vehicles for Position Verification in Vehicle Platooning.
Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

2016
ASIC Design of a Noisy Gradient Descent Bit Flip Decoder for 10GBASE-T Ethernet Standard.
CoRR, 2016

Noise-aided gradient descent bit-flipping decoders approaching maximum likelihood decoding.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

CNTFET-RFB: An Error Correction Implementation for Multi-valued CNTFET Logic.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2015
Decoding LDPC codes via Noisy Gradient Descent Bit-Flipping with Re-Decoding.
CoRR, 2015

Reliable gold code generators for GPS receivers.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Reducing the impact of internal upsets inside the correlation process in GPS Receivers.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

Reliable NCO carrier generators for GPS receivers.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

2014
Noisy Gradient Descent Bit-Flip Decoding for LDPC Codes.
IEEE Trans. Commun., 2014

Error Correction via Restorative Feedback in <i>M</i>-ary Logic Circuits.
J. Multiple Valued Log. Soft Comput., 2014

Stochastic Model Checking of Genetic Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2014

Decoding LDPC Codes With Locally Maximum-Likelihood Binary Messages.
IEEE Commun. Lett., 2014

2013
A Winner-Take-All circuit with improved accuracy and tolerance to mismatch and process variations.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Muller C-element based Decoder (MCD): A decoder against transient faults.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Performance of a high-speed transcutaneous link with error correction coding.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

CPS: an efficiency-motivated attack against autonomous vehicular transportation.
Proceedings of the Annual Computer Security Applications Conference, 2013

2012
Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-V<sub>T</sub> Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Design and Test of Genetic Circuits Using ${\tt iBioSim}$iBioSim.
IEEE Des. Test Comput., 2012

Error correction circuits for bio-implantable electronics.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A space-time redundancy technique for embedded stochastic error correction.
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

An LDPC decoding method for fault-tolerant digital logic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

125Mbps ultra-wideband system evaluation for cortical implant devices.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Utilizing stochastic model checking to analyze genetic circuits.
Proceedings of the 2012 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2012

2011
An Error Correction Method for Binary and Multiple-Valued Logic.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2010
Relaxation dynamics in stochastic iterative decoders.
IEEE Trans. Signal Process., 2010

iSSA: An incremental stochastic simulation algorithm for genetic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A Probabilistic LDPC-Coded Fault Compensation Technique for Reliable Nanoscale Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A dual-function mixed-signal circuit for LDPC encoding/decoding.
Integr., 2009

2008
Decoding LDPC Convolutional Codes on Markov Channels.
EURASIP J. Wirel. Commun. Netw., 2008

2007
Design for Testability of CMOS Analog Sum-Product Error-Control Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

2006
Low-voltage CMOS circuits for analog iterative decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

2005
Analog Soft Decoding for Multi-Level Memories.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

Stochastic iterative decoders.
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005

Digital built-in self-test of CMOS analog iterative decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An analog/digital mode-switching LDPC codec.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Density evolution analysis of device mismatch in analog decoders.
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004

A 0.8V CMOS analog decoder for an (8, 4, 4) extended Hamming code.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002
Cell library for automatic synthesis of analog error control decoders.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Analog decoding of product codes.
Proceedings of the 2001 IEEE Information Theory Workshop, 2001

Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001


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