Paul Muller

According to our database1, Paul Muller authored at least 12 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Game Plan: What AI can do for Football, and What Football can do for AI.
CoRR, 2020

Navigating the Landscape of Games.
CoRR, 2020

A Generalized Training Approach for Multiagent Learning.
Proceedings of the 8th International Conference on Learning Representations, 2020

2019
OpenSpiel: A Framework for Reinforcement Learning in Games.
CoRR, 2019

2009
A fully integrated 2×2 MIMO dual-band dual- mode direct-conversion CMOS transceiver for WiMAX/WLAN applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007
A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication.
IEEE J. Solid State Circuits, 2007

Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits.
J. Low Power Electron., 2007

2006
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A low-power, multichannel gated oscillator-based CDR for short-haul applications.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Jitter Tolerance Analysis of Clock and Data Recovery Circuits.
Proceedings of the Forum on specification and Design Languages, 2005

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.
Proceedings of the 2005 Design, 2005


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