Paul Muller
Affiliations:- Marvell Semiconductor, Santa Clara
- EPFL, Microelectronic Systems Laboratory
According to our database1,
Paul Muller
authored at least 25 papers
between 2004 and 2023.
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Bibliography
2023
Combining Tree-Search, Generative Models, and Nash Bargaining Concepts in Game-Theoretic Reinforcement Learning.
CoRR, 2023
Search-Improved Game-Theoretic Multiagent Reinforcement Learning in General and Negotiation Games.
Proceedings of the 2023 International Conference on Autonomous Agents and Multiagent Systems, 2023
2022
CoRR, 2022
CoRR, 2022
AI Commun., 2022
Proceedings of the International Conference on Machine Learning, 2022
Proceedings of the 21st International Conference on Autonomous Agents and Multiagent Systems, 2022
2021
J. Artif. Intell. Res., 2021
Proceedings of the 38th International Conference on Machine Learning, 2021
2020
Proceedings of the 8th International Conference on Learning Representations, 2020
2019
2009
A fully integrated 2×2 MIMO dual-band dual- mode direct-conversion CMOS transceiver for WiMAX/WLAN applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication.
IEEE J. Solid State Circuits, 2007
J. Low Power Electron., 2007
2006
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the Forum on specification and Design Languages, 2005
A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology.
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.
Proceedings of the 2005 Design, 2005
2004
A 4-channel 2.5Gb/s/channel 66dBΩ inductorless transimpedance amplifier [optical receiver applications].
Proceedings of the 33rd European Solid-State Circuits Conference, 2004