M. Akif Özkan

Orcid: 0000-0001-5067-2268

According to our database1, M. Akif Özkan authored at least 14 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
HipaccVX: wedding of OpenVX and DSL-based code generation.
J. Real Time Image Process., 2021

2020
AnyHLS: High-Level Synthesis With Partial Evaluation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Efficient parallel reduction on GPUs with Hipacc.
Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020

The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018
Loop Parallelization Techniques for FPGA Accelerator Synthesis.
J. Signal Process. Syst., 2018

Rapid Design of Real-Time Image Fusion on FPGA using HLS and Other Techniques.
Proceedings of the 15th IEEE/ACS International Conference on Computer Systems and Applications, 2018

2017
Generating FPGA-based image processing accelerators with Hipacc: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Hardware design and analysis of efficient loop coarsening and border handling for image processing.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
Hybrid code description for developing fast and resource efficient image processing architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

FPGA-based accelerator design from a domain-specific language.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Fast one- and two-pick fixed-priority selection and muxing circuits.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Using high-level synthesis for rapid design of video processing pipes.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016


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