Magali Bastian

According to our database1, Magali Bastian authored at least 22 papers between 2003 and 2009.

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Bibliography

2009
Analysis of Resistive-Open Defects in SRAM Sense Amplifiers.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A new design-for-test technique for SRAM core-cell stability faults.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs.
Proceedings of the 2008 IEEE International Test Conference, 2008

Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Design-for-Diagnosis Technique for SRAM Write Drivers.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits.
J. Electron. Test., 2007

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.
Proceedings of the 12th European Test Symposium, 2007

Slow write driver faults in 65nm SRAM technology: analysis and March test solution.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior.
Proceedings of the 16th Asian Test Symposium, 2007

2006
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.
J. Electron. Test., 2006

March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.
J. Electron. Test., 2005

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.
J. Electron. Test., 2005

Data Retention Fault in SRAM Memories: Analysis and Detection Procedures.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization.
Proceedings of the 10th European Test Symposium, 2005

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution.
Proceedings of the 9th European Test Symposium, 2004

Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Defect-oriented dynamic fault models for embedded-SRAMs.
Proceedings of the 8th European Test Workshop, 2003


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