Christian Landrault

According to our database, Christian Landrault authored at least 85 papers between 1978 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Is triple modular redundancy suitable for yield improvement?

Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

IET Comput. Digit. Tech., 2009

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash.

Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

J. Electron. Test., 2009

Something I Always Wanted to Know About Test, But Was Afraid to Ask.

Christian Landrault

Proceedings of the 14th IEEE European Test Symposium, 2009

2008

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.

Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault

J. Electron. Test., 2008

SoC Yield Improvement: Redundant Architectures to the Rescue?

Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 2008 IEEE International Test Conference, 2008

Yield Improvement, Fault-Tolerance to the Rescue?.

Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Using TMR Architectures for Yield Improvement.

Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Improving Diagnosis Resolution without Physical Information.

Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007

Editorial.

Christian Landrault, Erik Jan Marinissen

IET Comput. Digit. Tech., 2007

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.

Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.

Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

A concurrent approach for testing address decoder faults in eFlash memories.

Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga

Proceedings of the 2007 IEEE International Test Conference, 2007

DERRIC: A Tool for Unified Logic Diagnosis.

Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 12th European Test Symposium, 2007

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.

Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian

Proceedings of the 12th European Test Symposium, 2007

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.

Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 12th European Test Symposium, 2007

A Mixed Approach for Unified Logic Diagnosis.

Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Slow write driver faults in 65nm SRAM technology: analysis and March test solution.

Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Fast Bridging Fault Diagnosis using Logic Information.

Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 16th Asian Test Symposium, 2007

Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior.

Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 16th Asian Test Symposium, 2007

2006

A Gated Clock Scheme for Low Power Testing of Logic Cores.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

J. Electron. Test., 2006

An Overview of Failure Mechanisms in Embedded Flash Memories.

Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.

Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich

Proceedings of the IFIP VLSI-SoC 2006, 2006

Power-Aware Test Data Compression for Embedded IP Cores.

Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Serge Pravossoudovitch, Christian Landrault

Proceedings of the 15th Asian Test Symposium, 2006

2005

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.

Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.

Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault

Proceedings of the Integrated Circuit and System Design, 2005

2004

Power-Driven Routing-Constrained Scan Chain Design.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

J. Electron. Test., 2004

Design of Routing-Constrained Low Power Scan Chains.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 2004 Design, 2004

2003

A Unified DFT Approach for BIST and External Test.

Marie-Lise Flottes, Christian Landrault, A. Petitqueux

J. Electron. Test., 2003

A Ring Architecture Strategy for BIST Test Pattern Generation.

Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault

J. Electron. Test., 2003

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Guest Editorial.

Christian Landrault

J. Electron. Test., 2002

Hardware Generation of Random Single Input Change Test Sequences.

René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

J. Electron. Test., 2002

High Defect Coverage with Low-Power Test Sequences in a BIST Environment.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich

IEEE Des. Test Comput., 2002

On Using Efficient Test Sequences for BIST.

René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Power Driven Chaining of Flip-Flops in Scan Architectures.

Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test Power: a Big Issue in Large SOC Designs.

Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences.

Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

J. Electron. Test., 2001

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Generalized Distributed Comparison-Based System-Level Diagnosis.

Luiz Carlos Pessoa Albini, Elias P. Duarte Jr., Leonardo L. Giovanini, Marie-Lise Flottes, Christian Landrault, A. Petitqueux

Proceedings of the 2nd Latin American Test Workshop, 2001

A Gated Clock Scheme for Low Power Scan-Based BIST.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Random Adjacent Sequences: An Efficient Solution for Logic BIST.

René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the SOC Design Methodologies, 2001

Interconnect Capacitance Modelling in a VDSM CMOS Technology.

David Bernard, Christian Landrault, Pascal Nouet

Proceedings of the SOC Design Methodologies, 2001

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.

Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Low Power BIST by Filtering Non-Detecting Vectors.

Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos

J. Electron. Test., 2000

Hidden Markov and Independence Models with Patterns for Sequential BIST.

Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Low power BIST design by hypergraph partitioning: methodology and architectures.

Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

An adjacency-based test pattern generator for low power BIST design.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Design for sequential testability: an internal state reseeding approach for 100 % fault coverage.

Marie-Lise Flottes, Christian Landrault, A. Petitqueux

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits.

Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel

J. Electron. Test., 1999

A Test Vector Inhibiting Technique for Low Energy BIST Design.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Partial set for flip-flops based on state requirement for non-scan BIST scheme.

Marie-Lise Flottes, Christian Landrault, A. Petitqueux

Proceedings of the 4th European Test Workshop, 1999

On calculating efficient LFSR seeds for built-in self test.

Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault

Proceedings of the 4th European Test Workshop, 1999

Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts.

A. Toulouse, David Bernard, Christian Landrault, Pascal Nouet

Proceedings of the 1999 Design, 1999

Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

A BIST Structure to Test Delay Faults in a Scan Environment.

Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

A non-iterative gate resizing algorithm for high reduction in power consumption.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac

Integr., 1997

An optimized BIST test pattern generator for delay testing.

Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Hardware Test: Can We Learn from Software Testing?

J. Abraham, Phyllis G. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

On Using Machine Learning for Logic BIST.

Christophe Fagot, Patrick Girard, Christian Landrault

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

A gate resizing technique for high reduction in power consumption.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Automatic Testability Analysis of Boards and MCMs at Chip Level.

Marc Perbost, Ludovic Le Lan, Christian Landrault

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

A new test pattern generation method for delay fault testing.

S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits.

P. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Delay fault diagnosis in sequential circuits based on path tracing.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez

Integr., 1995

An advanced diagnostic method for delay faults in combinational faulty circuits.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch

J. Electron. Test., 1995

Diagnostic of path and gate delay faults in non-scan sequential circuits.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Is High-Level Test Synthesis Just Design for Test?

Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

A trace-based method for delay fault diagnosis in synchronous sequential circuits.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez

Proceedings of the 1995 European Design and Test Conference, 1995

Test configurations to enhance the testability of sequential circuits.

S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis.

D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation.

D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992

Delay-Fault Diagnosis by Critical-Path Tracing.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch

IEEE Des. Test Comput., 1992

BIST linear generator based on complemented outputs.

Lew Fock Chong Lew Yan Voon, Christian Dufaza, Christian Landrault

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors.

Lew Fock Chong Lew Yan Voon, Christian Dufaza, Christian Landrault

Proceedings of the Fifth International Conference on VLSI Design, 1992

A New Reliable Method for Delay-Fault Diagnosis.

Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch

Proceedings of the Fifth International Conference on VLSI Design, 1992

A Novel Approach to Delay-Fault Diagnosis.

Patrick Girard, Christian Landrault, Serge Pravossoudovitch

Proceedings of the 29th Design Automation Conference, 1992

1991

Fault modeling and fault equivalence in CMOS technology.

Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch

J. Electron. Test., 1991

1990

Fault modelling and fault equivalence in CMOS technology.

Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch

Proceedings of the European Design Automation Conference, 1990

1980

Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor.

Yves Crouzet, Christian Landrault

IEEE Trans. Computers, 1980

1978

Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults.

Alain Costes, Christian Landrault, Jean-Claude Laprie

IEEE Trans. Computers, 1978

SURF - A Program for Modeling and Reliability Prediction for Fault-Tolerant Computing Systems.

Christian Landrault, Jean-Claude Laprie

Proceedings of the Information Technology '78: Proceedings of the 3rd Jerusalem Conference on Information Technology (JCIT3), 1978