Bahar Asgari

Proceedings of the IEEE International Conference on Edge Computing and Communications, 2023

Context-Aware Task Handling in Resource-Constrained Robots with Virtualization.

[BibT_eX]

[DOI]

Nima Shoghi Ghaleshahi

Proceedings of the IEEE International Conference on Edge Computing and Communications, 2023

Creating Robust Deep Neural Networks with Coded Distributed Computing for IoT.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Edge Computing and Communications, 2023

2022

Maia: Matrix Inversion Acceleration Near Memory.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021

Efficiently Accelerating Sparse Problems by Enabling Stream Accesses to Memory using Hardware/Software Techniques.

[BibT_eX]

[DOI]

PhD thesis, 2021

MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System.

[BibT_eX]

[DOI]

Saibal Mukhopadhyay

J. Signal Process. Syst., 2021

Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Workload Characterization, 2021

FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Quantifying the design-space tradeoffs in autonomous drones.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020

Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads.

[BibT_eX]

[DOI]

CoRR, 2020

Edge-Tailored Perception: Fast Inferencing in-the-Edge with Efficient Model Distribution.

[BibT_eX]

[DOI]

CoRR, 2020

MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Proposing a Fast and Scalable Systolic Array for Matrix Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra.

[BibT_eX]

[DOI]

Nima Shoghi Ghaleshahi

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays.

[BibT_eX]

[DOI]

IEEE Micro, 2019

Characterizing the Deployment of Deep Neural Networks on Commercial Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Workload Characterization, 2019

Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM.

[BibT_eX]

[DOI]

Prashant J. Nair

Moinuddin K. Qureshi

Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems.

[BibT_eX]

[DOI]

Saibal Mukhopadhyay

CoRR, 2018

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube.

[BibT_eX]

[DOI]

Jeffrey S. Young

Burhan Ahmad Mudassar

Kartikay Garg

Tushar Krishna

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

2017

Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2017

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.

[BibT_eX]

[DOI]

Turkish J. Electr. Eng. Comput. Sci., 2017

Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube.

[BibT_eX]

[DOI]

Burhan Ahmad Mudassar

Saibal Mukhopadhyay