Ramin Rajaei
Orcid: 0000-0003-3851-9396
According to our database1,
Ramin Rajaei
authored at least 22 papers
between 2009 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2023
A Hybrid Optical-Electrical Analog Deep Learning Accelerator Using Incoherent Optical Signals.
ACM J. Emerg. Technol. Comput. Syst., April, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
IEEE Access, 2023
2022
A process variation resilient spintronic true random number generator for highly reliable hardware security applications.
Microelectron. J., 2022
Eva-CAM: A Circuit/Architecture-Level Evaluation Tool for General Content Addressable Memories.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
Low-Cost Sequential Logic Circuit Design Considering Single Event Double-Node Upsets and Single Event Transients.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2018
A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics.
J. Circuits Syst. Comput., 2018
2017
Highly reliable and low-power magnetic full-adder designs for nanoscale technologies.
Microelectron. Reliab., 2017
Single event double node upset tolerance in MOS/spintronic sequential and combinational logic circuits.
Microelectron. Reliab., 2017
Int. J. High Perform. Syst. Archit., 2017
Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.
Turkish J. Electr. Eng. Comput. Sci., 2017
2015
Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations.
J. Circuits Syst. Comput., 2015
2014
Soft error rate estimation for Combinational Logic in Presence of Single Event Multiple Transients.
J. Circuits Syst. Comput., 2014
2013
Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation.
Microelectron. Reliab., 2013
2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2009
Neurocomputing, 2009