Makihiko Katsuragi
  According to our database1,
  Makihiko Katsuragi
  authored at least 9 papers
  between 2015 and 2019.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
  2019
A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS.
    
  
    IEEE J. Solid State Circuits, 2019
    
  
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance.
    
  
    IEEE J. Solid State Circuits, 2019
    
  
  2018
    Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
    
  
  2017
A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS.
    
  
    IEICE Trans. Electron., 2017
    
  
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.
    
  
    Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
    
  
  2016
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad.
    
  
    IEEE J. Solid State Circuits, 2016
    
  
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB.
    
  
    IEEE J. Solid State Circuits, 2016
    
  
A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique.
    
  
    Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
    
  
  2015
A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB.
    
  
    Proceedings of the ESSCIRC Conference 2015, 2015