Tohru Kaneko

According to our database1, Tohru Kaneko authored at least 13 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A 0.85mm<sup>2</sup> BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance.
IEEE J. Solid State Circuits, 2019

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells.
IEICE Trans. Electron., 2018

A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits.
IEICE Trans. Electron., 2018

An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 0.85mm<sup>2</sup> BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input.
IEICE Trans. Electron., 2017

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture.
IEEE J. Solid State Circuits, 2016

A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency.
IEICE Trans. Electron., 2015

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015