Kengo Nakata

According to our database1, Kengo Nakata authored at least 20 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Revisiting a kNN-Based Image Classification System with High-Capacity Storage.
Proceedings of the Computer Vision - ECCV 2022, 2022

2021
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Weight Compression MAC Accelerator for Effective Inference of Deep Learning.
IEICE Trans. Electron., 2020

2019
Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer.
IEEE J. Solid State Circuits, 2018

A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS.
IEICE Trans. Electron., 2018


A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB.
IEEE J. Solid State Circuits, 2016

A 0.0055mm<sup>2</sup> 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI.
IEICE Trans. Electron., 2016

13.3 A 56Gb/s W-band CMOS wireless transceiver.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
14.1 A 0.048mm<sup>2</sup> 3mW synthesizable fractional-N PLL with a soft injection-locking technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular.
Proceedings of the ESSCIRC Conference 2015, 2015

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB.
Proceedings of the ESSCIRC Conference 2015, 2015


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