Kento Kimura

According to our database1, Kento Kimura authored at least 16 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance.
IEEE J. Solid State Circuits, 2019

2018
A 28.16-Gb/s Area-Efficient 60GHz CMOS Bi-Directional Transceiver for IEEE 802.11ay.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay.
IEEE J. Solid State Circuits, 2017

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017


2016
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture.
IEEE J. Solid State Circuits, 2016

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad.
IEEE J. Solid State Circuits, 2016

A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB.
IEEE J. Solid State Circuits, 2016

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
An AM-PM Noise Mitigation Technique in Class-C VCO.
IEICE Trans. Electron., 2015

19.5 An HCI-healing 60GHz CMOS transceiver.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB.
Proceedings of the ESSCIRC Conference 2015, 2015

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz.
Proceedings of the ESSCIRC 2014, 2014


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