Gabriele Tombesi
Orcid: 0000-0003-2590-0235
According to our database1,
Gabriele Tombesi authored at least 10 papers
between 2022 and 2026.
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Bibliography
2026
EPOCHS-1: A 12 nm Highly Heterogeneous Open-Source SoC With Distributed Coin-Based Power Management and Integrated Hybrid Voltage Regulation.
IEEE J. Solid State Circuits, May, 2026
A Coherence-Aware Runtime Reconfigurable System on Chip for Efficient Language Model Inference.
IEEE Micro, 2026
2025
FLIP2M: Flexible Intra-layer Parallelism and Inter-layer Pipelining for Multi-model AR/VR Workloads.
ACM Trans. Embed. Comput. Syst., 2025
ReconFormer: A Multi-Level Run-Time Reconfigurable System-on-Chip for Accelerating Transformers.
Proceedings of the 35th International Conference on Field-Programmable Logic and Applications, 2025
2024
Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures.
CoRR, 2024
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Des. Test, December, 2023
DECADES: A 67mm<sup>2</sup>, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022