Marcus Bednara

According to our database, Marcus Bednara authored at least 13 papers between 2000 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2025

Accelerating Linear Programming Performance: A Hardware-Software Co-Design Approach for the Simplex Method.

Marcus Bednara, Kristin Braun, Martina Kuchlbauer, Carsten Sigwarth

Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025

2018

Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach.

Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller, Umut Durak, Jürgen Becker

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017

WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach.

Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clément David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos S. Voros, Jürgen Becker

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2004

Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration.

Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

A New Approach for On-line Placement on Reconfigurable Devices.

Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003

Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms.

Marcus Bednara, Jürgen Teich

J. Supercomput., 2003

Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware.

Marcus Bednara, Klaus Danne, Markus Deppe, Oliver Oberschelp, Frank Slomka, Jürgen Teich

EURASIP J. Adv. Signal Process., 2003

FPGA designs of parallel high performance GF(2²³³) multipliers.

Cornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A High Performance VLIW Processor for Finite Field Arithmetic.

Cornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002

Generation of Distributed Loop Control.

Marcus Bednara, Frank Hannig, Jürgen Teich

Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Tradeoff analysis of FPGA based elliptic curve cryptography.

Marcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Reconfigurable Implementation of Elliptic Curve Crypto Algorithms.

Marcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich

Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2000

Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter.

Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka

Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000