Timo Stripf

According to our database1, Timo Stripf authored at least 21 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Embedded Multi-Core Code Generation with Cross-Layer Parallelization.
Proceedings of the 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2024

2019
Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications.
J. Aerosp. Inf. Syst., November, 2019

2018
A WCET-aware parallel programming model for predictability enhanced multi-core architectures.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2014
A Hierarchical Architecture Description for Flexible Multicore System Simulation.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Profile-Guided Compilation of Scilab Algorithms for Multiprocessor Systems.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Softwareframework für Prozessoren mit variablen Befehlssatzarchitekturen.
PhD thesis, 2013

Compiling Scilab to high performance embedded multicore systems.
Microprocess. Microsystems, 2013

A flexible implementation of the PSO algorithm for fine- and coarse-grained reconfigurable embedded systems.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Coarse-Grain Optimization and Code Generation for Embedded Multicore Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011
A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Architecture design space exploration of run-time scalable issue-width processors.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture.
Proceedings of the Design, Automation and Test in Europe, 2010

2008
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms.
Proceedings of the Design, Automation and Test in Europe, 2008


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