Mark Wijtvliet

Orcid: 0000-0002-4907-2334

According to our database1, Mark Wijtvliet authored at least 15 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

2022
Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

DELTA: DEsigning a stealthy trigger mechanism for analog hardware trojans and its detection analysis.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
CGRA-EAM - Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures.
ACM Trans. Reconfigurable Technol. Syst., 2021

2020
PR<sup>3</sup>: A system For radio-interferometry and radiation measurement on sounding rockets.
Microprocess. Microsystems, 2020

2019
Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2017
Loop Overhead Reduction Techniques for Coarse Grained Reconfigurable Architectures.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Coarse grained reconfigurable architectures in the past 25 years: Overview and classification.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

SFU-Driven Transparent Approximation Acceleration on GPUs.
Proceedings of the 2016 International Conference on Supercomputing, 2016

Multi-granular Arithmetic in a Coarse-Grain Reconfigurable Architecture.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Code Generation for Reconfigurable Explicit Datapath Architectures with LLVM.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

(AS)<sup>2</sup>: accelerator synthesis using algorithmic skeletons for rapid design space exploration.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013
MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013


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