Luc Waeijen

Orcid: 0000-0003-3491-0777

According to our database1, Luc Waeijen authored at least 22 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
CATS: Combined Activation and Temporal Suppression for Efficient Network Inference.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024

2023
Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators.
IEEE Trans. Parallel Distributed Syst., April, 2023

STAR: Sparse Thresholded Activation under partial-Regularization for Activation Sparsity Exploration.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

2022
How Flexible is Your Computing System?
ACM Trans. Embed. Comput. Syst., 2022

ARTS: An adaptive regularization training schedule for activation sparsity exploration.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
ConvFusion: A Model for Layer Fusion in Convolutional Neural Networks.
IEEE Access, 2021

How to exploit sparsity in RNNs on event-driven architectures.
Proceedings of the SCOPES '21: 24th International Workshop on Software and Compilers for Embedded Systems, Eindhoven, The Netherlands, November 1, 2021

2019
Schedule Synthesis for Halide Pipelines through Reuse Analysis.
ACM Trans. Archit. Code Optim., 2019

Automatic Memory-Efficient Scheduling of CNNs.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Bitwise Neural Network Acceleration: Opportunities and Challenges.
Proceedings of the 8th Mediterranean Conference on Embedded Computing, 2019

Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018
Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2016
Coarse grained reconfigurable architectures in the past 25 years: Overview and classification.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A configurable SIMD architecture with explicit datapath for intelligent learning.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Multi-granular Arithmetic in a Coarse-Grain Reconfigurable Architecture.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

MacSim: A MAC-Enabled High-Performance Low-Power SIMD Architecture.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Code Generation for Reconfigurable Explicit Datapath Architectures with LLVM.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
A Low-Energy Wide SIMD Architecture with Explicit Datapath.
J. Signal Process. Syst., 2015

A Co-Design Framework with OpenCL Support for Low-Energy Wide SIMD Processor.
J. Signal Process. Syst., 2015

2014
Reduction Operator for Wide-SIMDs Reconsidered.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
SIMD made explicit.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

OpenCL code generation for low energy wide SIMD architectures with explicit datapath.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013


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