Youngjoo Lee

Orcid: 0000-0002-2467-8276

According to our database1, Youngjoo Lee authored at least 111 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Intelligent MIMO Detection With Momentum-Induced Unfolded Layers.
IEEE Wirel. Commun. Lett., March, 2024

Multi-Group Multicasting Systems Using Multiple RISs.
CoRR, 2024

16.1 A 2.7-to-13.3μJ/boot/slot Flexible RNS-CKKS Processor in 28nm CMOS Technology for FHE-Based Privacy-Preserving Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
Block Orthogonal Sparse Superposition Codes for Ultra-Reliable Low-Latency Communications.
IEEE Trans. Commun., December, 2023

A Scalable Precoding Processor for Large-Scale MU-MIMO Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

A reproducible 3D convolutional neural network with dual attention module (3D-DAM) for Alzheimer's disease classification.
CoRR, 2023

Cost-Efficient GPIP Processing for Large-Scale Multi-User MIMO Systems.
IEEE Access, 2023

Optimizations of Privacy-Preserving DNN for Low-Latency Inference on Encrypted Data.
IEEE Access, 2023

A 2.35 Gb/s/mm<sup>2</sup> (7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Low-Complexity Phase Shift Design for IRS-Aided SU-MIMO Wireless Systems.
Proceedings of the 20th International SoC Design Conference, 2023

Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Analysis of Deep Learning-based MIMO Detectors.
Proceedings of the 14th International Conference on Information and Communication Technology Convergence, 2023

GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

TF-MVP: Novel Sparsity-Aware Transformer Accelerator with Mixed-Length Vector Pruning.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Low-Complexity Beamforming Optimization for IRS-Aided MU-MIMO Wireless Systems.
IEEE Trans. Veh. Technol., 2022

Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

CHAMP: Channel Merging Process for Cost-Efficient Highly-Pruned CNN Acceleration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Convolutional Neural Networks With Discrete Cosine Transform Features.
IEEE Trans. Computers, 2022

High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm.
IEEE J. Solid State Circuits, 2022

Simplified Ordered Statistic Decoding for Short-Length Linear Block Codes.
IEEE Commun. Lett., 2022

nuQmm: Quantized MatMul for Efficient Inference of Large-Scale Generative Language Models.
CoRR, 2022

A 1.1μs 1.56Gb/s/mm<sup>2</sup> Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Hardware Analysis of Channel Estimation Method for IRS-Aided MIMO Wireless Systems.
Proceedings of the 19th International SoC Design Conference, 2022

Fast Estimation of NTT/INTT Accelerator Costs for RNS-Based Homomorphic Encryption.
Proceedings of the 19th International SoC Design Conference, 2022

Algorithm-Hardware Co-Optimization for Cost-Efficient ML-based ISP Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A 2.86Gb/s Fully-Flexible MU-MIMO Processor for Jointly Optimizing User Selection, Power Allocation, and Precoding in 28nm CMOS Technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

Lightweight End-to-End Stress Recognition using Binarized CNN-LSTM Models.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

A Study On Reliable High-Speed HBC Enhanced by ECC for Wearable Neural Interfaces.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC Operator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Layerwise Buffer Voltage Scaling for Energy-Efficient Convolutional Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Novel Mobile Mechanism Design for an Obstacle-Overcoming Robot Using Rotating Spokes.
IEEE Access, 2021

Low-Cost Network Scheduling of 3D-CNN Processing for Embedded Action Recognition.
IEEE Access, 2021

Low-Complexity On-Device ECG Classifier using Binarized Neural Network.
Proceedings of the 18th International SoC Design Conference, 2021

Low-Complexity Voice Activity Detection Algorithm for Edge-Level Device.
Proceedings of the 18th International SoC Design Conference, 2021

Rapid Design Space Exploration of Near-Optimal Memory-Reduced DCNN Architecture Using Multiple Model Compression Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Low-Latency Polar Decoder Using Overlapped SCL Processing.
Proceedings of the IEEE International Conference on Acoustics, 2021

Approach to Improve the Performance Using Bit-level Sparsity in Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

Energy-Efficient Intelligent EPTS Device using Novel DCNN-Based Dynamic Sensor Activation.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

Utilizing Energy-Quality Trade-Off for Low-Cost ML-Based Compressive Sensing Reconstruction.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2020
Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Energy-Efficient Wearable EPTS Device Using On-Device DCNN Processing for Football Activity Classification.
Sensors, 2020

Shape-Morphing Wheel Design and Analysis for Step Climbing in High Speed Locomotion.
IEEE Robotics Autom. Lett., 2020

Low-Complexity DNN-Based End-to-End Automatic Speech Recognition using Low-Rank Approximation.
Proceedings of the International SoC Design Conference, 2020

High-Quality HTTP Live Streaming System for Limited Communication Bandwidth.
Proceedings of the International SoC Design Conference, 2020

Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Energy-Efficient Precoding Architecture for Multi-User MIMO Systems.
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

Hierarchical Approximate Memory for Deep Neural Network Applications.
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

2019
Rapid Balise Telegram Decoder With Modified LFSR Architecture for Train Protection Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Memory-Reduced Network Stacking for Edge-Level CNN Architecture With Structured Weight Pruning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance.
IEEE Access, 2019

Selective Deep Convolutional Neural Network for Low Cost Distorted Image Classification.
IEEE Access, 2019

Design of a Low-Power BLE5-Based Wearable Device for Tracking Movements of Football Players.
Proceedings of the 2019 International SoC Design Conference, 2019

WMixNet: An Energy-Scalable and Computationally Lightweight Deep Learning Accelerator.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Similarity-Based LSTM Architecture for Energy-Efficient Edge-Level Speech Recognition.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Ultra-Low-Latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Low-Complexity Dynamic Channel Scaling of Noise-Resilient CNN for Intelligent Edge Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

FPGA-Based Sparsity-Aware CNN Accelerator for Noise-Resilient Edge-Level Image Recognition.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

Multi-level Weight Indexing Scheme for Memory-Reduced Convolutional Neural Network.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions.
IEEE Access, 2018

Data Transfusion: Pairing Wearable Devices and Its Implication on Security for Internet of Things.
IEEE Access, 2018

Fixed-Point Quantization of 3D Convolutional Neural Networks for Energy-Efficient Action Recognition.
Proceedings of the International SoC Design Conference, 2018

Multi-Mode LSTM Network for Energy-Efficient Speech Recognition.
Proceedings of the International SoC Design Conference, 2018

A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Novel Folded-KES Architecture for High-Speed and Area-Efficient BCH Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

High-performance two-step lagrange interpolation technique for 4K UHD applications.
Proceedings of the International SoC Design Conference, 2017

POSTER: Watch Out Your Smart Watch When Paired.
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Low-Power Parallel Chien Search Architecture Using a Two-Step Approach.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems.
IEICE Trans. Electron., 2016

Area-efficient and high-speed binary divider architecture for bit-serial interfaces.
Proceedings of the International SoC Design Conference, 2016

Sharpness-aware real-time haze removal for advanced driver assistance systems.
Proceedings of the International SoC Design Conference, 2016

Group Information-Based Dimensionality Reduction via Canonical Correlation Analysis.
Proceedings of the Neural Information Processing - 23rd International Conference, 2016

FPGA-based real-time lane detection for advanced driver assistance systems.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Low-Complexity Tree Architecture for Finding the First Two Minima.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Efficient Parallel Architecture for Linear Feedback Shift Registers.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Binary tree optimization using genetic algorithm for multiclass support vector machine.
Expert Syst. Appl., 2015

2014
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives.
IEEE Trans. Very Large Scale Integr. Syst., 2014

7.3 Gb/s universal BCH encoder and decoder for SSD controllers.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.
IEEE J. Solid State Circuits, 2013

Application of density-based outlier detection to database activity monitoring.
Inf. Syst. Frontiers, 2013

Corrigendum to "Fast and efficient lung disease classification using hierarchical one-against-all support vector machine and cost-sensitive feature selection" [Comput. Biol. Med 42 (2012) 1157-1164].
Comput. Biol. Medicine, 2013

A 3Gb/s 2.08mm<sup>2</sup> 100b error-correcting BCH decoder in 0.13µm CMOS process.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Fast and efficient lung disease classification using hierarchical one-against-all support vector machine and cost-sensitive feature selection.
Comput. Biol. Medicine, 2012

6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Low-latency area-efficient decoding architecture for shortened reed-solomon codes.
Proceedings of the International SoC Design Conference, 2012

Small-area parallel syndrome calculation for strong BCH decoding.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011
Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Regional Context-Sensitive Support Vector Machine Classifier to Improve Automated Identification of Regional Patterns of Diffuse Interstitial Lung Disease.
J. Digit. Imaging, 2011

Statistical modeling of capacitor mismatch effects for successive approximation register ADCs.
Proceedings of the International SoC Design Conference, 2011

2010
Design of a Scalable and Programmable Sound Synthesizer.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low-complex BPSK demodulation using absolute comparison.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Development of an Automatic Classification System for Differentiation of Obstructive Lung Disease using HRCT.
J. Digit. Imaging, 2009

Performance testing of several classifiers for differentiating obstructive lung diseases based on texture analysis at high-resolution computerized tomography (HRCT).
Comput. Methods Programs Biomed., 2009

Improvement of computational efficiency using a cascade classification scheme for the classification of diffuse infiltrative lung disease on HRCT.
Proceedings of the Medical Imaging 2009: Computer-Aided Diagnosis, 2009

A computer-aided differential diagnosis between UIP and NSIP using automated assessment of the extent and distribution of regional disease patterns at HRCT: comparison with the radiologist's decision.
Proceedings of the Medical Imaging 2009: Computer-Aided Diagnosis, 2009

A Scalable and Programmable Sound Synthesizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Effect of various binning methods and ROI sizes on the accuracy of the automatic classification system for differentiation between diffuse infiltrative lung diseases on the basis of texture features at HRCT.
Proceedings of the Medical Imaging 2008: Image Processing, 2008

2007
Performance comparison of classifiers for differentiation among obstructive lung diseases based on features of texture analysis at HRCT.
Proceedings of the Medical Imaging 2007: Image Processing, 2007

The performance improvement of automatic classification among obstructive lung diseases on the basis of the features of shape analysis, in addition to texture analysis at HRCT.
Proceedings of the Medical Imaging 2007: Image Processing, 2007


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