Michitaro Kanamitsu

According to our database, Michitaro Kanamitsu authored at least 3 papers between 1991 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2006

A 130-nm CMOS 95-mm² 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput.

Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Keiichi Yoshida, Yoshinori Takase, Takayuki Yoshitake, Osamu Tsuchiya, Yoshinori Ikeda, Shunichi Narumi, Michitaro Kanamitsu, Kazuto Izawa, Kazunori Furusawa

IEICE Trans. Electron., 2006

1999

A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications.

Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi

IEEE J. Solid State Circuits, 1999

1991

A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current.

Katsuyuki Sato, Kanehide Kenmizaki, Shoji Kubono, Toshio Mochizuki, Hidetomo Aoyagi, Michitaro Kanamitsu, Soichi Kunito, Hiroyuki Uchida, Yoshihiko Yasu, Atsushi Ogishima, Sho Sano, Hiroshi Kawamoto

IEEE J. Solid State Circuits, November, 1991