Yoshihiko Yasu

According to our database1, Yoshihiko Yasu authored at least 6 papers between 2006 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2010
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS.
IEEE J. Solid State Circuits, 2010

2008
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.
IEEE J. Solid State Circuits, 2007

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution.
IEEE J. Solid State Circuits, 2007

2006
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006



  Loading...