Miles G. Canada

According to our database, Miles G. Canada authored at least 4 papers between 1998 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor.

Jürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles G. Canada

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2006

A 64B CPU Pair: Dual- and Single-Processor Chips.

Erwin B. Cohen, Norman J. Rohrer, Peter A. Sandon, Miles G. Canada, Cédric Lichtenau, Mathew I. Ringler, Paul Kartschoke, Robert Floyd, Jan Heaslip, M. Ross, Thomas Pflueger, Rolf B. Hilgendorf, Pete McCormick, Gerard Salem, J. Connor, Stephen F. Geissler, Dana Thygesen

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features.

Norman J. Rohrer, Cédric Lichtenau, Peter A. Sandon, Paul Kartschoke, Erwin B. Cohen, Miles G. Canada, Thomas Pflüger, Mathew I. Ringler, Rolf B. Hilgendorf, Stephen F. Geissler, Jeffrey S. Zimmerman

IEEE J. Solid State Circuits, 2005

1998

A 480-MHz RISC microprocessor in a 0.12-μm L_eff CMOS technology with copper interconnects.

Chekib Akrout, John Bialas, Miles G. Canada, Duane Cawthron, James Corr, Bijan Davari, Robert Floyd, Stephen F. Geissler, Ronald Goldblatt, Robert Houle, Paul Kartschoke, Diane Kramer, Pete McCormick, Norman J. Rohrer, Gerard Salem, Ronald Schulz, Lisa Su, Linda Whitney

IEEE J. Solid State Circuits, 1998