Juergen Pille
According to our database1,
Juergen Pille
authored at least 21 papers
between 2001 and 2018.
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Bibliography
2018
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018
2017
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015
A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2011
IEEE J. Solid State Circuits, 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2008
Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V.
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.
IBM J. Res. Dev., 2007
Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor.
IEEE J. Solid State Circuits, 2006
The vector fixed point unit of the synergistic processor element of the cell architecture processor.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
2001
IEEE J. Solid State Circuits, 2001