Bijan Davari

According to our database1, Bijan Davari authored at least 6 papers between 1995 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2002, "For contributions to high performance deep-submicron CMOS technology development.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2010
Workload and network-optimized computing systems.
IBM J. Res. Dev., 2010

2000
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro.
IEEE J. Solid State Circuits, 2000

1998
A 480-MHz RISC microprocessor in a 0.12-μm L<sub>eff</sub> CMOS technology with copper interconnects.
IEEE J. Solid State Circuits, 1998

1995
CMOS scaling for high performance and low power-the next ten years.
Proc. IEEE, 1995

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.
IBM J. Res. Dev., 1995

A half-micron CMOS logic generation.
IBM J. Res. Dev., 1995


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