David Hrusecky

According to our database, David Hrusecky authored at least 4 papers between 2010 and 2018.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2018

IBM POWER9 processor core.

Hung Q. Le, James Van Norstrand, Brian W. Thompto, José E. Moreira, Dung Q. Nguyen, David Hrusecky, Mike Genden, Michael Kroener

IBM J. Res. Dev., 2018

2015

IBM POWER8 processor core microarchitecture.

Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler

IBM J. Res. Dev., 2015

2011

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.

Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban

IEEE J. Solid State Circuits, 2011

2010

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor.

Jürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles G. Canada

Proceedings of the IEEE International Solid-State Circuits Conference, 2010