Otto A. Torreiter

According to our database, Otto A. Torreiter authored at least 10 papers between 1997 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology.

Alexander Fritsch, Rajiv V. Joshi, Sudipto Chakraborty, Holger Wetter, Uma Srinivasan, Matthew Hyde, Otto A. Torreiter, Michael Kugel, Dan Radko, Hyong Kim, Daniel J. Friedman

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2017

26.2 Power supply noise in a 22nm z13™ microprocessor.

Pierce I-Jen Chuang, Christos Vezyrtzis, Divya Pathak, Richard F. Rizzolo, Tobias Webel, Thomas Strach, Otto A. Torreiter, Preetham Lobo, Alper Buyuktosunoglu, Ramon Bertran, Michael S. Floyd, Malcolm S. Ware, Gerard Salem, Sean M. Carey, Phillip J. Restle

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology.

Philipp Salz, A. Frisch, Wolfgang Penth, J. Noack, T. Kalla, Rolf Sautter, Michael Kugel, Otto A. Torreiter, G. Sapp, Mike Lee, Eric Fluhr, A. Rozenfeld, Jürgen Pille, Dieter F. Wendel

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2015

A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction.

Alexander Fritsch, Michael Kugel, Rolf Sautter, Dieter F. Wendel, Juergen Pille, Otto A. Torreiter, Shankar Kalyanasundaram, Daniel A. Dobson

Proceedings of the ESSCIRC Conference 2015, 2015

2012

Electronic packaging of the IBM System z196 enterprise-class server processor cage.

Thomas Strach, Frank E. Bosco, Kenneth L. Christian, Kevin R. Covi, Martin Eckert, Gregory R. Edlund, Roland Frech, Hubert Harrer, Andreas Huber, Dierk Kaller, Martin Kindscher, A. Z. Muszynski, G. A. Peterson, Claudio Siviero, Jochen Supper, Otto A. Torreiter, Thomas-Michael Winkel

IBM J. Res. Dev., 2012

2010

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor.

Jürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles G. Canada

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V.

Juergen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel

IEEE J. Solid State Circuits, 2008

2007

Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V.

Jürgen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

Characterization of a 0.13 mum CMOS Link Chip using Time Resolved Emission (TRE).

Franco Stellari, Peilin Song, John Hryckowian, Otto A. Torreiter, Steve Wilson, Philip Wu, Alberto Tosi

Microelectron. Reliab., 2005

1997

Testing the Enterprise IBM System/390^TM Multi Processor.

Otto A. Torreiter, Ulrich Baur, Georg Goecke, Kevin Melocco

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997