Jose Paredes

Orcid: 0000-0001-7727-6505

According to our database1, Jose Paredes authored at least 9 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Pulsed Neural Network Plus Parallel Multi-core Approach to Solve Efficiently Big Shortest Path Problems.
Proceedings of the Advances in Soft Computing, 2019

2018
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018

2017
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015

IBM POWER8 circuit design and energy optimization.
IBM J. Res. Dev., 2015

2014
5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.
IEEE J. Solid State Circuits, 2011

2010
A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2007
Power-constrained high-frequency circuits for the IBM POWER6 microprocessor.
IBM J. Res. Dev., 2007


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