Mingqiang Huang
Orcid: 0000-0002-7794-3985
According to our database1,
Mingqiang Huang
authored at least 27 papers
between 2017 and 2025.
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Bibliography
2025
High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2025
EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2025
A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator.
CoRR, January, 2025
A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
An MLA-LLM Hardware Acceleration with Tensor-Train Decomposition on Group Vector Systolic Accelerator.
Proceedings of the 36th IEEE International Conference on Application-specific Systems, 2025
2024
IEEE Trans. Emerg. Top. Comput., 2024
EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models.
CoRR, 2024
LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024
A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
RRAM-Based Precision-Scaleable Computing-In-Memory Scheme and Its Error Correction Approach.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
Group Vectored Absolute-Value-Subtraction Cell Array for the Efficient Acceleration of AdderNet.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022
A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
A General-Purpose and Configurable Planar Data Processor for Energy-Efficient Pooling Computation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
AdderNet and its Minimalist Hardware Design for Energy-Efficient Artificial Intelligence.
CoRR, 2021
Hardware-Friendly Stochastic and Adaptive Learning in Memristor Convolutional Neural Networks.
Adv. Intell. Syst., 2021
Proceedings of the 38th International Conference on Machine Learning, 2021
2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017