Mitsuya Fukazawa

Orcid: 0000-0001-7979-5077

According to our database1, Mitsuya Fukazawa authored at least 12 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2021
A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction.
IEEE J. Solid State Circuits, 2021

2020
9.7 Background Multi-Rate LMS Calibration Circuit for 15MHz-BW 74dB-DR CT 2-2 MASH ΔΣ ADC in 28nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A High-Precision Analog Front End Integrated in a 32bit Microcontroller for Industrial Sensing Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2009
Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations.
IEICE Trans. Electron., 2009

2007
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs.
IEICE Trans. Electron., 2006

Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise.
IEICE Trans. Electron., 2006

Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A built-in power supply noise probe for digital LSIs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005


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