Kazuo Taki
According to our database1,
Kazuo Taki
authored at least 39 papers
between 1979 and 2007.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2007
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations.
IEICE Trans. Electron., 2007
A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System.
IEICE Trans. Electron., 2007
2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach.
IEICE Trans. Electron., 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits.
IEEE J. Solid State Circuits, 2005
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition.
IEICE Trans. Electron., 2005
2003
Syst. Comput. Jpn., 2003
2002
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2000
Proceedings of ASP-DAC 2000, 2000
1999
Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits.
Syst. Comput. Jpn., 1999
1998
A Survey for Pass-Transistor Logic Technologies - Recent Researches and Developments and Future Prospects (Embedded Tutorial).
Proceedings of the ASP-DAC '98, 1998
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998
1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1994
Parallel processing on the multi-PSI computer and its evaluation - a programming paradigm based on a small-grain highly concurrent object model.
Syst. Comput. Jpn., 1994
1992
Towards the General-Purpose Parallel Processing System, Panel Position Paper.
Proceedings of the International Conference on Fifth Generation Computer Systems. FGCS 1992, 1992
Parallel Inference Machine PIM.
Proceedings of the International Conference on Fifth Generation Computer Systems. FGCS 1992, 1992
Experimental Parallel Inference Software.
Proceedings of the International Conference on Fifth Generation Computer Systems. FGCS 1992, 1992
Parallel Logic Simulator based on Time Warp and its Evaluation.
Proceedings of the International Conference on Fifth Generation Computer Systems. FGCS 1992, 1992
Parallel and Distributed Implementation of Concurrent Logic Programming Language KL1.
Proceedings of the International Conference on Fifth Generation Computer Systems. FGCS 1992, 1992
LSI-CAD Programs on Parallel Inference Machine.
Proceedings of the International Conference on Fifth Generation Computer Systems. FGCS 1992, 1992
1991
Parallel Programming and Large-scale Applications in the FGCS Project.
Proceedings of the Logic Programming, 1991
1990
A load balancing mechanism for large scale multiprocessor systems and its implementation.
New Gener. Comput., 1990
A Multi-Level Load Balancing Scheme for OR-Parallel Exhaustive Search Programs on the Multi-PSI.
Proceedings of the Second ACM SIGPLAN Symposium on Princiles & Practice of Parallel Programming (PPOPP), 1990
1989
The FGCS Computing Architecture.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989
1988
Research and Development of the Parallel Inference System in the Intermediate Stage of the FGCS Project.
Proceedings of the International Conference on Fifth Generation Computer Systems, 1988
Overview of the Parallel Inference Machine Architecture (PIM).
Proceedings of the International Conference on Fifth Generation Computer Systems, 1988
Preliminary Evaluation of the Connection Network for the Multi-PSI System.
Proceedings of the 8th European Conference on Artificial Intelligence, 1988
1987
A Distributed Implementation of Flat GHC on the Multi-PSI.
Proceedings of the Logic Programming, 1987
Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), 1987
1986
Evaluation of PSI Micro-Interpreter.
Proceedings of the Spring COMPCON'86, 1986
1984
A Microprogrammed Interpreter for the Personal Sequential Inference Machine.
Proceedings of the International Conference on Fifth Generation Computer Systems, 1984
Hardware Design and Implementation of the Personal Sequential Inference Machine (PSI).
Proceedings of the International Conference on Fifth Generation Computer Systems, 1984
1983
New Gener. Comput., 1983
The Personal Sequential Inference Machine (PSI): Its Design and Machine Architecture.
Proceedings of the Logic Programming Workshop '83, Praia da Falésia, Algarve, Portugal, 26 June, 1983
1979
The Experimental LISP Machine.
Proceedings of the Sixth International Joint Conference on Artificial Intelligence, 1979